1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices. Even more specifically, this invention relates to a method to read flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices to reduce oxide stress.
2. Discussion of the Related Art
A microelectronic Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) device includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory device are made small by omitting select transistors that would enable the cells to be erased independently. As a result, all of the cells must be erased simultaneously as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary "1" or "0" or to erase all of the cells as a block.
The cells are connected in a rectangular array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together to a common source. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying typically 8-9 volts to the control gate, approximately 5 volts to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell can be erased in several ways. In one arrangement, applying typically 12 volts to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Alternatively, applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can erase a cell.
The cell is read by applying typically 5 volts to the control gate, 1-2 volts to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (.apprxeq.4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (.apprxeq.2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
During read the voltages applied to the terminals cause oxide stress in the memory cell. Oxide stress can cause electrons to tunnel across the tunnel oxide to the floating gate. This causes the threshold voltage, V.sub.t, to increase and is referred to as charge gain. The cause of the oxide stress is the control gate voltage that is applied causes current to flow in the cell and is given approximately by the equation EQU I=k(V.sub.GS -V.sub.t).sup.n,
where V.sub.GS is the voltage from the gate to the source, k is a proportional constant and V.sub.t is the threshold voltage of the cell. It can be seen from the equation that increasing V.sub.GS increases I. Unfortunately, increasing V.sub.GS also increases the oxide stress as can be seen from the equation for the oxide voltage V.sub.FG. The voltage V.sub.FG is proportional to the control gate voltage V.sub.CG as follows: EQU V.sub.FG .about.V.sub.CG (C.sub.gate oxide)/(C.sub.gate oxide +C.sub.tunnel oxide)
where C.sub.gate oxide is the capacitance of the gate oxide and C.sub.tunnel oxide is the capacitance of the tunnel oxide. The control gate voltage V.sub.CG .about.V.sub.GS =&gt;oxide stress voltage-V.sub.FG .about.V.sub.GS (C.sub.gate oxide)/(C.sub.gate oxide +C.sub.tunnel oxide). To properly read the cell a certain minimum current is required. From the equation, EQU I=k(V.sub.GS -V.sub.t).sup.n,
the voltage V.sub.GS would need to be some minimum value. Another alternative to maintain the current and reducing V.sub.GS would be to decrease V.sub.t. The direct way to do this would be to increase the positive charge on the floating gate. In that case V.sub.FG would increase and the oxide stress would increase so this alternative would not be a good approach.
Therefore, what is needed is a method of reducing the V.sub.t without increasing the oxide stress.